除了SystemVerilog中的defparam之外，有没有一种很好的方法来覆盖测试中的testbench参数

module test_tb();

  
   parameter int  NUM_LAYERS                       = 3;
   parameter int  NUM_NS_PER_LAYER[NUM_LAYERS]     = '{8,8,8};


      initial
        begin
         #100;
         $display ("NUM_LAYERS is %d and NUM_NS_PER_LAYER is %p", NUM_LAYERS, NUM_NS_PER_LAYER);
         $display ("NUM_LAYERS is %d ", NUM_LAYERS);
        end
endmodule


module test();

   localparam int NS                                             = 1;
   localparam int NSP[NS]                                        = '{4};
   defparam test_tb.NUM_LAYERS                                   = 1;
   // The following 2 lines fail with simulators but some simulators will accept it if I uncomment the next line and comment out the line after it.
   //defparam test_tb.NUM_NS_PER_LAYER                             = NSP;
   defparam test_tb.NUM_NS_PER_LAYER                             = '{4};


endmodule